1. Field of the Invention
The present invention relates to a test apparatus configured to test a semiconductor device.
2. Description of the Related Art
After a semiconductor device is manufactured, a semiconductor test apparatus (which will also be referred to simply as a “test apparatus” hereafter) is used in order to test whether or not the semiconductor device thus manufactured operates normally. The test apparatus is configured to receive a signal (signal under test) output from a DUT (device under test), and to compare the signal under test with an expected value so as to judge the quality (Pass/Fail) of the DUT. Also, the test apparatus is configured to measure the amplitude margin and/or the timing margin of the signal under test.
In some cases, a PLL (Phase Locked Loop) circuit or a DLL (Delay Locked Loop) circuit configured to receive a clock signal from an external circuit, i.e., a test apparatus, and to generate an internal clock signal using the clock signal as a reference signal is built into such a DUT. In order to test such a DUT, the test apparatus is configured to output a vector pattern to a normal pin of the DUT, and to supply a clock signal to a clock terminal of the DUT.
Description will be made below regarding a situation in which, after a test is executed using a given test pattern, the test condition is switched, and a test is executed under the test condition thus switched. In this case, such a test condition switching operation requires a certain amount of switching time. If the supply of the clock signal to the DUT is stopped in the test condition switching operation, the PLL circuit or otherwise the DLL circuit switches from the locked state to the unlocked state. Thus, before a test pattern is supplied in the next operation, there is a need to again lock the PLL circuit or the DLL circuit, leading to a problem of a long test time.
Conceivable methods used to solve such a problem include a method in which, during a period of time in which the supply of a test pattern is stopped, i.e., during a period of time in which the test condition is switched, a clock signal is continuously output to the clock input pin of the DUT. This ensures that the PLL circuit or the DLL circuit built into the DUT is kept in the locked state. FIG. 1 is a flowchart showing an operation for maintaining the locked state of the PLL/DLL circuit built into the DUT.
Also, a transmission method in which a clock signal is embedded in a data signal has become popular. Examples of such a transmission method include a CDR (Clock Data Recovery) method, and a packet method. In a case of testing a DUT employing such a transmission method, the PLL circuit or the DLL circuit cannot be maintained in the locked state using the aforementioned test method. This is because, when the test pattern is stopped in the test condition switching, the clock signal, which is configured as data embedded in the data signal, is not supplied.